加入收藏
 免费注册
 用户登陆
首页 展示 供求 职场 技术 智造 职业 活动 视点 品牌 镨社区
今天是:2024年5月15日 星期三   您现在位于: 首页 →  技术 → 行业标准(半导体器件)
Open NAND Flash Interface Specification
2007/2/1 16:41:26    产通学院,365PR NET

开放式NAND闪存接口规范(ONFi 2.0版)于2月27日发布,主要内容:

1. Introduction ....................... 1
1.1. Goals and Objectives .................. 1
1.2. Re 1
1.3. Definitions, abbreviations, and conventions................... 1
1.3.1. Definitions and Abbreviations ............ 1
1.3.2. Conventions .................... 4


2. Physical Interface .................... 7
2.1. TSOP-48 and WSOP-48 Pin Assignments........................ 7
2.2. LGA-52 Pad Assignments....................... 10
2.3. BGA-63 Ball Assignments....................... 11
2.4. BGA-100 Ball Assignments..................... 15
2.5. Signal Descriptions ................................. 19
2.6. CE# Signal Requirements....................... 24
2.6.1. Source Synchronous Data Interface Requirements.................. 24
2.7. Absolute Maximum DC Ratings .............. 24
2.8. Recommended DC Operating Conditions.............................. 25
2.8.1. I/O Power (VccQ) and I/O Ground (VssQ)........................ 25
2.9. AC Overshoot/Undershoot Requirements.......................... 25
2.10. DC and Operating Characteristics....... 26
2.11. Calculating Pin Capacitance ............... 28
2.12. Staggered Power-up............................ 28
2.13. Independent Data Buses..................... 29
2.14. Bus Width Requirements..................... 30
2.15. Ready/Busy (R/B#) Requirements ...... 30
2.15.1. Power-On Requirements.............. 30
2.15.2. R/B# and SR[6] Relationship ....... 31
2.16. Write Protect......................... 31


3. Memory Organization ..................... 32
3.1. Addressing ............................ 33
3.1.1. Interleaved Addressing .................... 34
3.1.2. Logical Unit Selection ...................... 34
3.1.3. Multiple LUN Operation Restrictions 34
3.2. Factory Defect Mapping.......................... 35
3.2.1. Device Requirements....................... 35
3.2.2. Host Requirements .......................... 35
3.3. Discovery and Initialization...................... 36
3.3.1. CE# Discovery ................................. 36
3.3.2. Target Initialization........................... 37
3.4. Partial Page Programming...................... 38
3.4.1. Requirements................................... 38
3.4.2. Host Discovery................................. 38


4. Data Interface and Timing .......................... 39
4.1. Data Interface Types............................... 39
4.1.1. Signal Function Reassignment ........ 39
4.1.2. Bus State .......................... 40
4.1.3. Source Synchronous and Repeat Bytes.............. 41
4.1.4. Data Interface / Timing Mode Transitions............... 42
4.2. Timing Parameters.......................... 43
4.2.1. General Timings......................... 43
4.2.2. Asynchronous ......................... 44
4.2.3. Source Synchronous................ 49
4.3. Timing Diagrams............................ 60
4.3.1. Asynchronous ....................... 60
4.3.2. Source Synchronous................ 67
4.4. Command Examples...................... 76
4.4.1. Asynchronous .................................. 76
4.4.2. Source Synchronous........................ 79


5. Command Definition ................................... 84
5.1. Command Set ......................................... 84
5.2. Command Descriptions........................... 86
5.3. Reset Definition....................................... 89
5.4. Synchronous Reset Definition................. 89
5.5. Read ID Definition ................................... 90
5.6. Read Parameter Page Definition ............ 91
5.6.1. Parameter Page Data Structure Definition ............... 94
5.7. Read Unique ID Definition..................... 106
5.8. Block Erase Definition ........................... 108
5.9. Read Status Definition .......................... 108
5.10. Read Status Enhanced Definition ..... 109
5.11. Read Status and Read Status Enhanced required usage........... 109
5.12. Status Field Definition..................... 110
5.13. Read Definition ............................ 111
5.14. Read Cache Definition....................... 113
5.15. Page Program Definition ................... 117
5.16. Page Cache Program Definition........ 119
5.17. Copyback Definition........................... 122
5.18. Change Read Column Definition....... 127
5.19. Change Write Column Definition ....... 127
5.20. Set Features Definition...................... 128
5.21. Get Features Definition...................... 130
5.22. Feature Parameter Definitions .......... 130
5.22.1. Timing Mode............................... 131
5.22.2. I/O Drive Strength....................... 131


6. Interleaved Operations .................... 133
6.1. Requirements.............................. 133
6.2. Status Register Behavior ...................... 134
6.3. Interleaved Page Program .................... 134
6.4. Interleaved Copyback Program ............ 137
6.5. Interleaved Block Erase ........................ 139


7. Behavioral Flows ............................. 140
7.1. Target behavioral flows ......................... 140
7.1.1. Variables ................................ 140
7.1.2. Idle states........................... 140
7.1.3. Idle Read states ............................. 142
7.1.4. Reset command states .................. 143
7.1.5. Read ID command states .............. 144
7.1.6. Read Parameter Page command states........................ 145
7.1.7. Read Unique ID command states.. 147
7.1.8. Page Program and Page Cache Program command states............ 147
7.1.9. Block Erase command states ........ 149
7.1.10. Read command states ............... 151
7.1.11. Set Features command states ... 153
7.1.12. Get Features command states... 154
7.1.13. Read Status command states .... 154
7.1.14. Read Status Enhanced command states..................... 155
7.2. LUN behavioral flows ..................... 156
7.2.1. Variables .................... 156
7.2.2. Idle command states...................... 156
7.2.3. Idle Read states ................... 158
7.2.4. Status states ....................... 158
7.2.5. Reset states ........................ 160
7.2.6. Block Erase command states ........ 160
7.2.7. Read command states................... 162
7.2.8. Page Program and Page Cache Program command states ................ 163

A. Sample Code for CRC-16 (Informative) ... 167
B. Spare Size Recommendations (Informative).................... 169

下载开放式NAND闪存接口规范(ONFi 2.0版),请访问http://www.onfi.org/docs/ONFI%202_0%20Gold.pdf

→ 『关闭窗口』
 pr_room
 [ → 我要发表 ]
上篇文章:ONFi(开放式NAND闪存接口工作组)
下篇文章:Sematech (美国半导体制造技术战略联盟)
→ 主题所属分类:  行业标准 → 半导体器件
 热门文章
 如何申请EtherCAT技术协会(ETG)会员资格 (167028)
 台北国际计算机展(COMPUTEX 2015)参展商名… (104325)
 上海市集成电路行业协会(SICA) (90733)
 USB-IF Members Company List (82657)
 第十七届中国专利优秀奖项目名单(507项) (74300)
 台北国际计算机展(COMPUTEX 2015)参展商名… (67890)
 苹果授权MFi制造商名单-Authorized MFi Lic… (67219)
 中国130家太阳能光伏组件企业介绍(3) (55226)
 PLC论坛 (52158)
 中国130家太阳能光伏组件企业介绍(2) (48504)
 最近更新
 英特尔用于下一代先进封装的玻璃基板(Glass Subs… (4月29日)
 EUV光刻技术回眸:Trumpf、Zeiss和ASML的… (4月3日)
 为Al设计的NPU与其他处理器共同加速生成式AI体验 (3月9日)
 英特尔为未来数据中心开发的处理器芯片新技术 (2月23日)
 压电技术使手机屏幕直接变成高质量话筒 (2月14日)
 PCB基础知识及设计软件概述 (2月2日)
 国家文化和科技融合示范基地名单(含第五批) (1月24日)
 国家文化和科技融合示范基地认定管理办法(试行) (1月24日)
 隐身衣逐步走进现实:光学隐身衣、电磁波隐身衣 (10月30日)
 电子电路常用电子元件名称缩写及中英文对照 (10月17日)
 文章搜索
搜索选项:            
  → 评论内容 (点击查看)
您是否还没有 注册 或还没有 登陆 本站?!
关于我们 ┋ 免责声明 ┋ 产品与服务 ┋ 联系我们 ┋ About 365PR ┋ Join 365PR
Copyright @ 2005-2008 365pr.net Ltd. All Rights Reserved. 深圳市产通互联网有限公司 版权所有
E-mail:postmaster@365pr.net 不良信息举报 备案号:粤ICP备06070889号