Vivace于2005年成立，致力于创造全新的安全视频处理芯片，以满足下一代用户对电子产品的需求。通过对自定义处理器、高集成化固件以及硅验证IP的结合，Vivace正努力创造出高性能芯片，满足媒体处理器的高标准要求。

Vivace芯片可支持包括H264/MPEG4 AVC、MPEG4 ASP、Windows Media 9、MPEG2及VC-1在内的多种视频压缩标准和包括AES、DES、3-DES及DVB CSA在内的多种解码标准。

因应业务发展需要，现在诚聘以下人员加盟：

  
招聘职位：模拟集成电路设计工程师（Analog IC Design Engineer）
职责：
模拟集成电路IP核设计，负责Video D/A转换器、A/D转换器、PLL等模拟IP的开发，包括技术规格定义，前后端设计，IP评价与标准化等。
要求：
（1）微电子或电子工程类专业
 (2) 熟悉CMOS 器件的设计和加工工艺
（3）熟悉模拟电路，参加过经典模拟电路（Amplifier，ADC，DAC 或PLL等）的设计流程，熟悉音视频领域的模拟电路（如Video D/A）设计者优先考虑。
（4）精通模拟电路设计的基本工具，如HSPICE、SPECTRE、HSIM、Matlab等，熟悉IC设计流程的后端EDA工具
（5）具有较强的理解能力和协作能力。
Duties:
Responsible for analog IP core design such as Video D/A converter, PLL and A/D converter , including specification definition , front-end and back-end design, IP evaluation and standardize.
Requirements:
(1) Microelectronic or electronic engineering major ;
(2)Familiar with CMOS devices’ design and process technologies;
(3) familiar with analog circuits, participated design flow of typical circuit designs (such as Amplifier, ADC, DAC or PLL, etc.), the candidate familiar with Audio/Video analog circuit (such as Video DAC or PLL) will be given priority.
(4) Skillfully use basic EDA software and analysis tools for analog domain, such as HSPICE, Spectre, HSIM, MatLab, etc, familiar with back-end design tools ;
(5) Good understanding and cooperation? spirit.
 

招聘职位：数字前端设计工程师（Digital FE Design Engineer）
职责：
负责面向SoC应用的CPU核及其周边模块的前端电路设计、功能与时序验证、可测性设计；配合后端设计工程师实现数字模块的时序收敛与功耗收敛。
要求：
（1）电子工程或计算机专业本科以上学历；
（2）熟悉前端设计的整个开发流程及相关EDA工具（Simulation、Synthesis 和Timing Analysis）；熟练掌握Verilog等设计语言；有较强的系统设计和数字逻辑电路设计能力。
（3）熟悉通用微处理器体系结构及其验证环境，有RISC CPU、LCD Controller等设计经验者优先考虑，
（4）具有较强的、理解能力和协作能力。
Duties:
Responsible for front-end design, functional and timing verification, and testing design of CPU core and peripherals for SoC application. A candidate needs to coordinate with back-end design engineers toward a closure of digital module’s timing and power convergence.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with front-end design flow and EDA tools (relating to simulation, synthesis and timing analysis); Skillfully use Verilog hardware description language; Have strong ability of system and digital logic design;
(3) Familiar with the architecture of universal micro processor as well as its verification environment, the candidate who has design experience of RISC CPU or LCD controller will be given priority;
(4)Good understanding and cooperation? spirit.
 

招聘职位：DSP技术支持工程师（DSP Application Engineer）
职责：
负责先进的DSP核销售技术支持；帮助客户利用DSP技术和工具开发客户产品。
要求：
（1）电子工程或计算机专业本科以上学历；
（2）熟悉DSP应用，具有DSP领域的开发经验；
（3）了解基本的IC设计流程，使用过硬件描述语言Verilog
（4）有较强的学习能力，理解能力和协作能力。
（5）良好的英语能力，能够阅读和书写英文技术文档
（6）熟悉Java、Jbuilder和VLIW体系结构者优先考虑。
Duties:
Responsible for sales support of an advanced DSP core, help customers smoothly employ our DSP technology and tool suite to develop their products.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with DSP application, have development experience relating to DSP ; (3) Understand basic IC design flow, be capable to use hardware description language Verilog ;
(4) Strong ability of study，good understanding and cooperation spirit.
(5) Good English knowledge, be capable to read and write technical documents;
(6)The candidate familiar with Java, Jbuilder and VLIW architecture will be given priority
 

招聘职位：SoC集成支持工程师（SoC Integration Engineer）
职责：
负责SoC集成技术支持；帮助客户基于CPU或DSP技术平台开发客户的SoC产品。
要求：
（1）电子工程或计算机专业本科以上学历；
（2）熟悉以IP为基础的SoC集成方案，熟悉DSP应用和CPU平台应用技术；
（3）熟悉SoC设计流程和RTL设计
（4）有较强的学习能力，理解能力和协作能力。
（5）良好的英语能力，能够阅读和书写英文技术文档。
Duties:
Responsible for technical support of SoC integration, help customers develop their SoC products based on our CPU or DSP technology platform.
Requirements:
(1) BS of electronic engineering , computer science, or above ;
(2)Familiar with IP-based SoC integration solution, familiar with DSP and CPU platform application;
(3) Familiar with SoC? design flow and RTL deisgn ;
(4) Strong ability of study，good understanding and cooperation spirit.
(5) Good English knowledge, be capable to read and write technical documents.
 

招聘职位：应用工程师（Application Engineer）
职责：
负责公司VSP产品的应用技术支持。包括
（1）针对产品的应用方案，支持从芯片产品的开发系统、参考系统、应用系统到客户（系统设计公司）的过程；
（2）对市场部门运作提供技术支持；
（3）相关产品技术调研等等。
要求：
熟悉系统级设计流程；熟练使用Cadence OrCAD/Allegro流程进行系统级设计；了解基于32位嵌入式SoC芯片搭建的系统；了解视频编解码相关芯片使用；了解电源管理芯片的使用；有广泛的应用工程知识，能与软、硬件设计，用户界面设计、安规测试、结构设计等专业人员沟通和交流。熟悉音视频DSP器件和手持系统设计和应用者优先
Duties:
Responsible for SoC product applications and technical supports. Oriented to SoC products’ application solutions, with supporting activities range from the chip’s development system, reference system, application system, customers (system design house) designs through entire design chain and industrial processes;
Requirements:
Familiar with system-level design flow; master cadence OrCAD/Allegro tool for system-level designs; master system integration which is based on a 32-bit embedded SoC; understand video codec chips’ applications; understand power management components’ applications and their PCB level solutions. The candidate should possess a broad range of experience in application engineering and ability to communicate effectively with professionals who engage in hardware, software design, user interface design, safety test and structure design. A candidate should be rich in hands-on design and assembly experience, skillfully uses logic analyzer, oscillograph, etc. Ones who are familiar with A/V DSP devices and application of FPGA will be much preferred.

 
招聘职位：嵌入式软件工程师（Embedded System Software Engineer）
职责：
负责开发使用公司VSP产品的不同系统上的相关软件；包括Linux操作系统、驱动程序、专用测试程序和应用软件；针对不同的用户方案，进行相关项目的软件开发，包括驱动程序以及针对专用协议（比如 移动电视标准）的软件设计；和嵌入式系统设计工程师配合完成系统的联调。
要求：
精通C/C++语言；熟悉嵌入式Linux操作系统或Windows CE操作系统，有操作系统优化、裁减等项目经验；有通用应用软件（比如UI）开发经验；有基于嵌入式操作系统的驱动程序开发经验；对通用硬件平台（比如 ARM）有一定使用基础；熟练使用相对应的开发与调试工具；熟悉团队开发工具与版本控制工具的使用；熟悉网络与音视频相关DSP数据标准与开发者优先。
Duties:
Develop embedded software for the company’s proprietary SoC products. Software work involves operation system, driver programs, dedicated test and benchmark, upon application software. Assist and coordinate system engineers’ and IC designers’ development work, together accomplish implementation and test of a system product (solutions, applications and prototypes);
Requirements:
Being skillful in C/C++ programming, familiar with embedded Linux or Windows CE operating systems, skillfully uses related development and debugging tools. The candidate should be understating and being familiar with principle and operations of processor development systems, master program and data version control tools. Familiarity with network and A/V DSP data standards is preferred
 

招聘职位：嵌入式系统硬件设计工程师（Embedded Hardware System Design Engineer）
职责：
负责设计基于公司SoC产品，针对不同应用的板级解决方案；配合SoC产品开发与测试设计相关电路。完成从产品方案制订到系统级原理图设计的全过程；配合PCB布线工程师完成符合时序与功耗要求的PCB设计；配合嵌入式软件工程师与SoC设计工程师完成软硬件的联合调试。
要求：
熟悉系统级设计流程；熟练使用Cadence OrCAD/Allegro流程进行系统级设计；了解基于32位嵌入式SoC芯片搭建的系统；了解电源管理芯片的使用；丰富的动手调试经验；熟练使用逻辑分析仪、示波器等测试手段进行硬件调试。熟悉音视频DSP器件和FPGA应用者优先。
Duties:
Develop systems based on the company’s SoC products, towards the products’ various PCB-level solutions. Cooperate with SoC product designers in test fixture development. Accomplish entire solution developments, from specifications to system design; cooperate with PCB layout engineers to complete designs that fulfill targeted timing and power performance. Cooperate with embedded software engineers and SoC engineers to accomplish hardware/software joint implementation.
Requirements:
Familiar with system-level design flow; master cadence OrCAD/Allegro tool for system-level designs; master system integration which is based on a 32-bit embedded SoC; understand power management components’ applications and their PCB level solutions. A candidate should be rich in hands-on design and assembly experience, skillfully uses logic analyzer, oscillograph, etc. Ones who are familiar with A/V DSP devices and application of FPGA will be much preferred
 

招聘职位：算法工程师（Algorithm Engineer）
职责：
负责通信系统基带算法的设计、优化；对硬件实现及系统应用过程进行支持，协助完成测试验证。
要求：
通信、电子及相关专业硕士；精通信号处理知识，具有一定的理论基础；熟练使用matlab，熟悉JAVA、C语言；两年以上移动通信系统开发经验；有DSP开发经验或熟悉verilog尤佳；具备良好的英语读写能力，有良好的团队合作及钻研精神。
Duties:
Responsible for designing and optimization of communication baseband signal processing algorithm, supporting the hardware designing and system application, assisting relational testing, verification;
Requirements:
MS. in EE, communication or related engineering fields; familiar with algorithms of signal processing; hands-on with Matlab, familiar with C, JAVA; at least 2 years experiences in mobile communication system development; knowledge on DSP, verilog , is a plus ; excellent English communication skills, be good at English reading
 

招聘职位：系统工程师(软件)（System Engineer (software)）
职责：
完成通信系统中软件部分的程序设计；搭建完整的系统开发、验证环境；完成软件及硬件代码的协同验证；负责项目开发过程中的版本管理。
要求：
计算机、电子、通信及相关专业硕士；有一年以上实际的通信系统项目经验，精通C、JAVA；对ARM开发，常见总线接口如I2C、SPI有一定了解；熟悉verilog尤佳；具备良好的英语读写能力，有良好的团队合作及钻研精神。
Duties:
Responsible for designing software part in communication system; constructing testing flat, performing? system verifying and version controlling.
Requirements:
MS. in computer science ,EE, communication or related engineering fields; have practical experience in communication development; familiar with C, JAVA; knowledge on ARM development.I2C, SPI etc; knowledge on? verilog , is a plus ; excellent English communication skills, be good at English reading.
 

招聘职位：高级数字前端设计工程师（Digital Front-end Design Engineer）
职责：
负责通信系统复杂数字模块的RTL生成、功能验证；配合后端设计工程师实现数字模块的时序收敛与功耗收敛。
要求：
电子、通信及相关专业硕士；两年以上工作经验；熟练使用Verilog硬件描述语言进行可综合设计；了解ESL描述与验证；能熟练使用主流设计工具完成复杂数字模块的设计与验证；有复杂数字系统的FPGA实现经验,具备良好的英语读写能力，有良好的团队合作及钻研精神。
Duties:
Responsible for front-end design, functional verification. coordinate with back-end design engineers toward a closure of digital module’s timing and power convergence.
Requirements:
MS. in computer science ,EE, communication or related engineering fields;? skillfully use Verilog hardware description language for logic design and synthesize; understand ESL descriptions and related verification, can skillfully use mainstream design tools for accomplishing complex digital modules’design and verification
 
 
招聘职位：数字前端设计工程师（Digital Front-end Design Engineer)
职责：
负责通信系统复杂数字模块的RTL生成、功能验证。
要求：
电子、通信及相关专业学士；一年以上工作经验；熟练使用Verilog硬件描述语言进行可综合设计；能熟练使用主流设计工具完成数字模块的设计与验证,具备良好的英语读写能力，有良好的团队合作及钻研精神。
Duties:
Responsible for front-end design, functional verification.
Requirements:
Bachelor in computer science ,EE, communication or related engineering fields; one year practical experience,? skillfully use Verilog hardware description language for logic design and synthesizable ; can skillfully use mainstream design tools for accomplishing digital modules’ design and verification
 
 
招聘职位：系统工程师（System Engineer）
职责：
完成基带芯片外围接口设计，与后端工程师配合完成基于FPGA的测试验证。
要求：
电子、通信及相关专业学士；两年以上工作经验；对模拟芯片及ADC的各种参数有一定了解；熟悉常见的接口协议如I2C、SPI等，熟练使用Verilog硬件描述语言，对数字系统的FPGA验证有所了解,具备良好的英语读写能力，有良好的团队合作及钻研精神。
Duties:
Responsible specifying IO of baseband processor, coordination with back-end engineer to?? accomplish verifying on FPGA.
Requirements:
Bachelor in computer science ,EE, communication or related engineering fields; two year practical experience; familiar with? general parameters of RF chip and ADC; knowledge on I2C,SPI etc.;? familiar with verilog ; good knowledge on verifying on FPGA is a plus ; excellent English communication skills, be good at English reading.
 

了解进一步信息，请访问http://www.vivace.com.cn/job/job.html，或联系Vivace公司：
E-mail: job@vivace.com.cn
联系电话: 82358482-620