富迪科技中国上海工作机会
TEL:021-52381010-806
Email:beths@fortemedia.com.cn

Soc Design and Verification Engineer

Job Description:
(1) Build Soc simulation environment, testbench and test cases base on the Test plan and design Spec
(2) Verify the logic design through simulation
(3) STA, formal verification, Post-layout simulation
(3) Do RTL coding for project need
(4) DFT correlative job and ATE support

Qualifications:
(1) BSEE minimum 2+year or MSEE minimum 1+year correlative work experience
(2) Familiar of system Verilog, EDA tools and IC design floor and SoC verification methodology
(3) Master the Perl, TCL or C_SHELL script language
(4) Have good ability of team work and making documentation
(5) Have the embedded software development on DSP or MCU is Plus
 

FPGA Design and Verification Engineer
 
Job Description:
(1) Build FPGA verification environment and test cases for the Soc chip before tape out
(2) Optimize and Map the logic design to FPGA for the verification of Soc design
(3) CO-verification HW and SW on FPGA platform at real time mode

Qualifications:
(1) BSEE minimum 3+year or MSEE minimum 2+year correlative work experience
(2) Familiar of Verilog, Synplify, ISE and FPGA design floor
(3) Knowledgeable in DSP, MCU architecture, CODEC design
(4) Have good ability of team work and making documentation
(5) Have the Vertix-2 or Vertix-4 experience is plus
 

Senior System Verification Engineer

Job Description:
(1) Engineering Board and FPGA target board design, review and debug
(2) Build the Stress test and silicon debug environment
(3) Silicon bring-up, debug,? regress, ?cover corner bugs and failure analysis
(4) Verify Soc chip design on real application level base on FPGA (before tape out) and sample chip

Qualifications:
(1) BSEE minimum 4+year or MSEE minimum 3+year correlative work experience
(2) Familiar of system design and debugging
(3) Master the method of Silicon debugging, failure analysis, and stress test
(4) Have good ability of team work and making documentation
(5) Have the experience of Voice or Handset system design or DSP algorithm development is Plus