天利半导体集团公司成立于2004年6月，总部位于美国，亚太营运中心位于香港，中国区总部位于深圳，是由美国硅谷集成电路设计资深专家创建以及来自北大、清华的数字、模拟电路的专家加盟，目前旗下全资子公司天利半导体（深圳）有限公司和北京方益集成电路设计有限公司。

天利半导体设计、开发、销售平板显示屏幕的驱动芯片，其业务涵盖集成电路设计的全部流程, 包括IC设计、工艺开发、IC封装技术、IC测试、产品应用开发、产品验证、特性化测试及失效分析。

天利半导体以市场需求为导向，结合公司的技术优势，相继推出了系列MSTN、CSTN、TFT、OLED、TCON屏幕显示驱动芯片，并获得多项国内发明专利，各项技术指标均达到同类国际知名品牌的标准，具有卓越的性价比。

天利半导体秉承“融资上下游产业，打造中国完整IC产业链”的企业发展战略，全资收购京东方旗下IC设计公司北京方益集成电路设计有限公司并与各大晶圆厂，封装厂、模块设计制造企业、终端制造商结成紧密的战略伙伴合作和投资关系，形成市场、技术、资金、管理的良性互动，实现产品在技术、价格、交付能力、客户服务等方面的整体竞争力，全力打造中国最大的TFT-LCD驱动IC供货商。
 
天利半导体现有如下职位空缺：
 
招聘职位：ASIC验证测试工程师
招聘人数： 3 人
有效时间： 2008-12-31
要求： ASIC验证测试部经理Logic Verification Engineer
1)Job Function
A)In charge of verification and testing of ASIC chips.
B)Write test and verification spec for mixed signal chips.
C)Generate test and verification plan.
D)Manage a group of test and verification engineers.
2)Candidates must have the following qualifications.
A)At least 2 years RTL and Vera coding experience
B)Experience of managing a group of engineers..
C)Able to write and use test-bench to test RTL blocks.
D)Able to program FPGA to test logic blocks.
E)Must have strong logic thinking ability.
F)Strong ability to enforce methodology.
G)ASIC debugging experience preferred.

招聘职位：ASIC全定制版图设计
招聘人数： 3 人
有效时间： 2008-12-31 
要求： ASIC全定制版图设计VLSI Backend Design Engineer
1) Job Function
A) In charge of circuit custom layout design.
B) Responsible for block level floorplanning.
2) Candidates must have the following qualifications.
A) B.S Degree in EE or Computer Science. M.S. preferred.
B) 2-5 years experience in IC design.
C) Experienced in floor planning.
D) Familiar with cadence place and route tools.
E) Experienced in writing scripts for place and route.
F) Experienced in writing scripts for gate net-list synthesis.
G) Custom designed circuit layout experience.
H) Able to correctly model parasitic loading.
I) Aware of all the electric design issues involved including cross talk, IR drop, and electro-migration issues.

招聘职位：ASIC逻辑设计工程师 Logic Design Engineer
招聘人数： 5 人
有效时间： 2008-12-31
要求： 学 历：本科
工作年限：二年以上
薪水范围：面议
职位描述：
Job Function
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.
B)Define micro architecture of digital part of the mixed signal IC.
Candidates must have the following qualifications.
A)2 years RTL coding experience
B)Understanding of concept of state-machine.
C)Understanding of the concept of timing. Able to perform static timing analysis.
D)Familiar with VCS or NC-Verilog
E)Able to write and use test-bench to test RTL blocks.
F)Able to program FPGA to test logic blocks.

招聘职位：IC模拟电路设计经理
招聘人数： 3 人
有效时间： 2008-12-31
要求： Job Function
A)Design consumer electronics mixed signal IC
B)Responsible for product definition and micro architecture.
Candidates must have the following qualifications.
A)B.S Degree in EE or Computer Science. M.S. preferred.
B)Recent experience of designing TFT or STN LCD driver chip is preferred.
C)Aware of most of the issues involved including circuit design, module, glass panel, foundry interface, packaging, ESD design, testing.
D)Familiar with mixed signal design and verification flow.
E)Strong analog design background.
F)2-5 years experience in IC design.
G)Layout experienc(LVS/DRC)
H)Detailed knowledge of reference voltage circuit, dc-dc charge pump circuit, and oscillator circuit design.
I)Familiar with SPICE and mixed-signal simulation tools

招聘职位：ASIC逻辑设计经理
招聘人数： 5 人
有效时间： 2008-12-31
要求： Job Function
A)Design digital circuit blocks using RTL coding in mixed signal IC chips.
B)Write RTL code for custom designed blocks such as SRAM and adder blocks.
C)Define micro architecture of digital part of the mixed signal IC.
D)Verification of the logic blocks using test bench and Vera.
E)Use FPGA to validate the designed blocks.
F)Write synthesis script to generate gate level netlist.
G)Analyze timing for synthesized blocks.
Candidates must have the following qualifications.
A)2 years RTL coding experience
B)Understanding of concept of state-machine.
C)Understanding of the concept of timing. Able to perform static timing analysis.
D)Familiar with VCS or NC-Verilog
E)Able to write and use test-bench to test RTL blocks.
F)Able to program FPGA to test logic blocks.

联系人：金先生
http://www.tlsemi.com/html/appjob.php
EMAI：jinguohong@tlsemi.com